{"id":83,"date":"2012-08-13T19:45:00","date_gmt":"2012-08-14T00:45:00","guid":{"rendered":"http:\/\/www.graygoo.net\/blog\/?p=83"},"modified":"2012-08-20T10:23:45","modified_gmt":"2012-08-20T15:23:45","slug":"vhdl-type-conversions","status":"publish","type":"post","link":"http:\/\/www.graygoo.net\/blog\/2012\/08\/vhdl-type-conversions\/","title":{"rendered":"VHDL type conversions"},"content":{"rendered":"

I have been learning VHDL<\/a> for simulation and synthesis lately. Coming from a Verilog background, one of the biggest differences between Verilog and VHDL is the latter’s type system. VHDL is strongly typed, even compared to C or C++. Every signal has a type, and the compiler will tolerate very little ambiguity between types. It is fair to say you will get nowhere with VHDL until you are comfortable working with them.<\/p>\n

VHDL supports many types, but you can get by with a small number of them for logic synthesis, including\u00a0std_logic, std_logic_vector, signed, unsigned, integer. The types are defined by IEEE 1164<\/a>, implemented in the std_logic_1164 library. While we’re on the subject, you will also want to use the numeric_std and possibly std_logic_unsigned libraries for helper functions.<\/p>\n

Example header:<\/p>\n

library IEEE;\r\nuse IEEE.std_logic_1164.all;      -- for logic types\r\nuse IEEE.numeric_std.all;         -- for signed\/unsigned arithmetic\r\nuse IEEE.std_logic_unsigned.all;  -- for std_logic_vector arithmetic<\/pre>\nI will briefly describe the types:<\/p>\n
std_logic is a single multi-valued logic bit. Most often, it will be driven either as ‘0’ (logic 0\/false) or ‘1’ (logic 1\/true). It supports 1-bit logical operations.<\/p>\n
Example declaration and initialization:<\/p>\nsignal s0 : std_logic := '1';<\/pre>\nstd_logic_vector, signed, unsigned are all bit vectors, or fixed size arrays of std_logic bits. They should be thought of primarily as bit vectors, and not numbers in the usual sense. A limited number of arithmetic functions are available, and the operands must be\u00a0explicitly\u00a0<\/em>cast or converted into the same type.<\/p>\n
Example\u00a0declaration and initialization (note double quotes):<\/p>\nsignal v1: std_logic_vector(3 downto 0) := \"1011\";  -- binary 1011\r\nsignal u1: unsigned(3 downto 0) := \"1011\";          -- decimal 11 (unsigned)\r\nsignal s1: signed(3 downto 0) := \"1011\";            -- decimal -5 (signed 2's complement)<\/pre>\nstd_logic_vector supports bitwise logical operations. It will also support unsigned arithmetic with the ieee.std_logic_unsigned package. signed and unsigned support arithmetic with numeric_std.<\/p>\n
The integer is a different animal. It is a number. Unless constrained, it will be in the full range defined by the implementation (currently signed 32-bit). The integer will need to be constrained for the integer to be converted to a smaller number of wires. Integers are more intuitive to work with internally, but all interfaces should be implemented using one of the vector types (preferably std_logic_vector).<\/p>\n
Example:<\/p>\nsignal i1: integer range 0 to 15; -- 4 bits<\/pre>\nType Conversions<\/h2>\nIn general, one of the array types can be cast to another type of the same size:<\/p>\nu1 <= unsigned(v1);          -- unsigned cast\r\ns1 <= signed(u1);            -- signed cast\r\nv1 <= std_logic_vector(s1);  -- std_logic_vector cast<\/pre>\nA conversion function (to_x) must be used to convert between integers and signed\/unsigned types. Two operations, a conversion and a cast, are required to convert between integer and std_logic_vector. Note that unlike the cast, the conversion function takes a second argument, length, to constrain the integer to a fixed number of bits.<\/p>\n
Example:<\/p>\nu1 <= to_unsigned(i1, 4);    -- unsigned conversion\r\ns1 <= to_signed(i1, 4);      -- signed conversion\r\nv1 <= std_logic_vector(u1);  -- std_logic_vector cast\r\n\r\ni1 <= to_integer(s1);        -- integer conversion<\/pre>\nThe takeaway from this is that for logic synthesis, I find it useful to think of VHDL bottom-up as a symbolic representation of discrete logic (ports and wires) rather than top-down as a logical implementation of the high-level design. <\/p>\n","protected":false},"excerpt":{"rendered":"I have been learning VHDL for simulation and synthesis lately. Coming from a Verilog background, one of the biggest differences between Verilog and VHDL is the latter’s type system. VHDL is strongly typed, even compared to C or C++. Every … Continue reading →<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[20],"class_list":["post-83","post","type-post","status-publish","format-standard","hentry","category-ugoo","tag-vhdl"],"_links":{"self":[{"href":"http:\/\/www.graygoo.net\/blog\/wp-json\/wp\/v2\/posts\/83","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/www.graygoo.net\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/www.graygoo.net\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/www.graygoo.net\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.graygoo.net\/blog\/wp-json\/wp\/v2\/comments?post=83"}],"version-history":[{"count":0,"href":"http:\/\/www.graygoo.net\/blog\/wp-json\/wp\/v2\/posts\/83\/revisions"}],"wp:attachment":[{"href":"http:\/\/www.graygoo.net\/blog\/wp-json\/wp\/v2\/media?parent=83"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/www.graygoo.net\/blog\/wp-json\/wp\/v2\/categories?post=83"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/www.graygoo.net\/blog\/wp-json\/wp\/v2\/tags?post=83"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}